The present invention is generally directed to a system for detecting metastability errors in successive approximation analog-to-digital converters and method thereof. More specifically, the subject system and method provide for a successive approximation analog-to-digital converter (ADC) having a comparator unit that includes a circuit for output of a signal responsive to the comparator latching a result. Further, the system and method are directed to a successive approximation analog-to-digital converter that includes a metastability detection and correction circuit that monitors the signal output by the comparator unit responsive to the comparator latching a result and detects a metastable event by an absence of that signal by the end of a portion of the ADC conversion time period for a bit. Responsive to detection of a metastable event, a logic circuit is provided for generating a correct conversion code at the output of the ADC. If no metastable event is detected during a conversion cycle of the ADC, the metastability detection and correction circuit outputs the conversion codes determined by the comparator.
Of the various types of analog-to-digital converters (ADC), the successive approximation ADC architecture has long been favored in many applications requiring high speed, low power consumption, and suitably high conversion resolution. The successive approximation ADC that is shown in FIG. 1 is a design that has been recently patented by the present inventor and provides a good starting point for understanding the invention described herein. For conversion to an n-bit digital word, the successive approximation ADC 10, shown in FIG. 1, generally operates to sample an analog input signal voltage via input 118 and then carry out a binary search for the corresponding quantized level to be coded via the n-bit word. The binary search is carried out over each of the bit positions in the n-bit word, with a comparator 124 compares the sampled input signal voltage provided from a sample and hold included in element 122, against a succession of voltage reference levels provided from the switched capacitor digital-to-analog converter (DAC) of element 122. This comparison is thereby made for each successive “state” of the n-bit word as it is updated, bit-by-bit, in the successive approximation register (SAR) 116 of the successive approximation ADC 10.
The voltage reference levels for the states are successively provided according to an SAR logic state machine 102 of the successive approximation ADC 10. The levels are set for each state by the internal reference DAC 122 relative to a reference voltage VREF provided by the reference generator 120. For each state, the SAR logic state machine prescribes the voltage reference level according to the quantization value then defined by the n-bit digital word.
A successive approximation ADC processing cycle thus includes a sampling phase followed by a conversion phase, during which a series of bit determinations are successively made. This cycle is repeated for subsequent samples of the input analog signal. With advances in device technologies, such as deep submicron semiconductor technologies, there is an increasing demand for greater speed of the successive approximation ADC processing cycle.
One of the limitations to increasing the processing speed is the time required for the comparator to make a valid decision. When there is a small differential in the input to the comparator, it will take longer for the comparator to make its decision and which if not made within the time allotted, will result in a large conversion error at random times. One solution, provided in the successive approximation ADC of FIG. 1, includes a circuit in the comparator 124 that detects when the comparator has made a decision and in response thereto outputs a data ready signal on line 112 to the clock generator 104, which then causes the SAR logic state machine 102 to advance to the next state. In this way, as shown in the timing diagram of FIG. 2, the processing is asynchronous with the clocking of the SAR logic state machine 102 and the comparator 124 being adaptively generated by the clock generator 104. In this manner, bit determinations are only delayed when required and otherwise proceeds at a maximum rate in accordance with settling and propagation times of the components of the successive approximation ADC.
One known method of producing high speed successive approximation ADCs is to place multiple ADCs in parallel, as shown in FIG. 3, and clocking the converters 300a-300n in sequence, each converting a respective analog voltage supplied from a sample and hold circuit (not shown) on input line 306. When using parallel ADCs 300a-300n, it is advantageous to have the ADCs share a common reference 302 for good gain matching between the converters. When sharing the reference 302, it is advantageous to clock each ADC 300a-300n with a common clock, input on line 304, so that the voltage reference is perturbed at the clock period and has the same time to settle after this clock before each comparator is sampled in the parallel ADCs 300a-300n. 
With the asynchronous successive approximation ADC of FIG. 1, the comparator has a data ready output which indicates when the comparator 124 has made a decision. When the differential inputs of the comparator are close together in value, near the metastable point, it will take a longer period of time for the comparator to make a decision and for the data ready line to be asserted. Once the data ready line is asserted, the clock generator circuitry 104 then generates a new clock pulse to advance the SAR circuitry 116 to the next state to determine the next bit. The problem with this approach is that the time at which the SAR logic state machine 102 advances to the next state is uncertain, which means that the time that the switched capacitor DAC 122 is switched to the next setting is uncertain.
Since when the switched capacitor DAC switches, it puts a transient load on the reference generator 120, the noise on this voltage reference occurs at indeterminate times. Therefore, if this reference is shared between a number of parallel ADCs 300a-300n, as shown in FIG. 3, the noise caused by one ADC may corrupt the reference voltage of one of the other ADCs when it's comparator is clocked, resulting in an erroneous output.